Ultra-fast characterization of transient gate oxide trapping in SiC MOSFETs

One of the most important issues that limits the performance and reliability of SiC power MOSFETs is the threshold voltage and drain current instability under normal operation conditions. This phenomenon has been recently studied using conventional dc measurements. In this work, we studied the threshold voltage and drain current instability in state-of-the-art 4H-SiC MOSFETs using fast I- V measurements. Fast I- V measurements reveal the full extent of the instability, underestimated by the dc measurements. Furthermore, fast measurements allow the separation of negative and positive bias stress effects. Post oxidation annealing in NO was found to passivate the oxide traps and dramatically reduce instability. A physical model involving fast transient charge trapping and detrapping at and near the SiC/SiO₂ interface is proposed.