Spatial Monitoring of I/O Interconnection Nets in Flip-Chip Packages

Here, we introduce a novel method for the real-time spatial monitoring of I/O interconnection nets in flip-flop packages. Resistance changes in 39 I/O nets are observed simultaneously to produce a spatial profile of the relative degradations of the solder ball joints, interconnection lines, and transistor gates. Location-specific TTF profiles are generated from the degradation data to show the impact of the I/O nets in the context of their placement on the chip. The system succeeds in formulating a clear trend of resistance increase even in relatively mild constant temperature stress conditions. Test results of four temperatures from 80 °C to 120 °C show a dominant degradation pattern strongly influenced by BTI aging demonstrating an acute vulnerability in the pass gates to voltage and temperature stress. The proposed compact spatial monitor solution can be integrated into virtually all chip orientations. The outcome of this study can assist in foreseeing system vulnerabilities in a large spectrum of packaging and advanced packaging orientations in field applications.