@inproceedings{0f692be550784e4384004814f888a695,
title = "Setting quality control requirements to balance between Cycle Time and Yield in a semiconductor production line",
abstract = "We consider a semiconductor production line in which production stations are afflicted by a defect deposition process and immediately followed by an inspection step. We propose to integrate operational aspects into quality considerations by formulating a Cycle Time (CT) versus Yield trade off. We connect the two performance measures through the determination of the limit for defects at the inspection step. We extend former results to a tandem production line and present an optimal greedy algorithm that provides the Pareto-optimal set of Upper Control Limit (UCL) values for the line. The obtained model enables decision makers to knowingly sacrifice Yield to shorten CT and vice versa.",
author = "Miri Gilenson and Michael Hassoun and Liron Yedidsion",
note = "Publisher Copyright: {\textcopyright} 2014 IEEE.; 2014 Winter Simulation Conference, WSC 2014 ; Conference date: 07-12-2014 Through 10-12-2014",
year = "2015",
month = jan,
day = "23",
doi = "10.1109/WSC.2014.7020086",
language = "אנגלית",
series = "Proceedings - Winter Simulation Conference",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "2422--2433",
editor = "Andreas Tolk and Levent Yilmaz and Diallo, \{Saikou Y.\} and Ryzhov, \{Ilya O.\}",
booktitle = "Proceedings of the 2014 Winter Simulation Conference, WSC 2014",
address = "ארצות הברית",
}