TY - JOUR
T1 - Reliability simulation and circuit-failure analysis in analog and mixed-signal applications
AU - Yan, Baoguang
AU - Qin, Jin
AU - Dai, Jun
AU - Fan, Qingguo
AU - Bernstein, Joseph B.
N1 - Funding Information:
Manuscript received November 13, 2008; revised February 17, 2009. First published April 14, 2009; current version published September 2, 2009. This work was supported in part by NIST, by the AVSI Consortium, and by the Office of Naval Research. B. Yan, J. Qin, J. Dai, and Q. Fan are with the Reliability Engineering, University of Maryland, College Park, MD 20742 USA (e-mail: [email protected]). J. B. Bernstein is with the Reliability Engineering, University of Maryland, College Park, MD 20742 USA, and also with Bar Ilan University, Ramat-Gan 52900, Israel (e-mail: [email protected]). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TDMR.2009.2020740
PY - 2009/9
Y1 - 2009/9
N2 - In this paper, an effective and efficient methodology for reliability simulation is developed to bridge the gap between device-level reliability and that at product level. For the first time, reliability and circuit-failure behaviors under analog and mixed-signal operating conditions are simulated and analyzed with a high-speed Flash analog-to-digital converter (ADC) circuit developed in advanced CMOS technology. We demonstrate how the failure rate at circuit-level integrating multiple failure mechanisms is determined as a function of operating voltage and temperature. The results show that the dominant failure mechanism and failure rate could be changed by operating conditions. Based on the complete analysis of the ADC circuit operating under normal condition, negative bias temperature instability (NBTI) is the predominant failure mechanism in normal analog and mixed-signal applications, and failure rate increases with the elevated temperature. The impact of NBTI on circuit performance is addressed in detail. Two different types of degradation caused by NBTI are investigated: output voltage degradation and delay. The simulation results are verified by the field data. After exploring the reliability behaviors, a design for reliability methodologies is proposed and classified into two categories: device and circuit levels. This paper shreds light for the circuit life estimation and further reliable design.
AB - In this paper, an effective and efficient methodology for reliability simulation is developed to bridge the gap between device-level reliability and that at product level. For the first time, reliability and circuit-failure behaviors under analog and mixed-signal operating conditions are simulated and analyzed with a high-speed Flash analog-to-digital converter (ADC) circuit developed in advanced CMOS technology. We demonstrate how the failure rate at circuit-level integrating multiple failure mechanisms is determined as a function of operating voltage and temperature. The results show that the dominant failure mechanism and failure rate could be changed by operating conditions. Based on the complete analysis of the ADC circuit operating under normal condition, negative bias temperature instability (NBTI) is the predominant failure mechanism in normal analog and mixed-signal applications, and failure rate increases with the elevated temperature. The impact of NBTI on circuit performance is addressed in detail. Two different types of degradation caused by NBTI are investigated: output voltage degradation and delay. The simulation results are verified by the field data. After exploring the reliability behaviors, a design for reliability methodologies is proposed and classified into two categories: device and circuit levels. This paper shreds light for the circuit life estimation and further reliable design.
KW - Analog and mixed-signal operation
KW - Circuit reliability
KW - Failure mechanisms
KW - Reliability simulation
KW - Reliable design
UR - http://www.scopus.com/inward/record.url?scp=70249120776&partnerID=8YFLogxK
U2 - 10.1109/TDMR.2009.2020740
DO - 10.1109/TDMR.2009.2020740
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AN - SCOPUS:70249120776
SN - 1530-4388
VL - 9
SP - 339
EP - 347
JO - IEEE Transactions on Device and Materials Reliability
JF - IEEE Transactions on Device and Materials Reliability
IS - 3
M1 - 4814578
ER -