TY - GEN
T1 - Impact of device scaling on deep sub-micron transistor reliability - A study of reliability trends using SRAM
AU - White, Mark
AU - Bing, Huang
AU - Jin, Qin
AU - Gur, Zvi
AU - Talmor, Michael
AU - Yuan, Chen
AU - Heidecker, Jason
AU - Nguyen, Duc
AU - Bernstein, Joseph
PY - 2005
Y1 - 2005
N2 - As microelectronics are scaled in to the deep submicron regime, users of advanced technology CMOS, particularly in high-reliability applications, should reassess how scaling effects impact long-term reliability. An experimental based reliability study of industrial grade SRAMs, consisting of three different technology nodes, is proposed to substantiate current acceleration models for temperature and voltage life-stress relationships. This reliability study utilizes Step-Stress techniques to evaluate memory technologies (0.25μm, 0.1 μm, and 0.13μm) embedded in many of today's high-reliability space/aerospace applications. Two acceleration modeling approaches are presented to relate experimental FIT calculations to Mfr's qualification data.
AB - As microelectronics are scaled in to the deep submicron regime, users of advanced technology CMOS, particularly in high-reliability applications, should reassess how scaling effects impact long-term reliability. An experimental based reliability study of industrial grade SRAMs, consisting of three different technology nodes, is proposed to substantiate current acceleration models for temperature and voltage life-stress relationships. This reliability study utilizes Step-Stress techniques to evaluate memory technologies (0.25μm, 0.1 μm, and 0.13μm) embedded in many of today's high-reliability space/aerospace applications. Two acceleration modeling approaches are presented to relate experimental FIT calculations to Mfr's qualification data.
UR - https://www.scopus.com/pages/publications/33847745405
U2 - 10.1109/IRWS.2005.1609574
DO - 10.1109/IRWS.2005.1609574
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AN - SCOPUS:33847745405
SN - 0780389921
SN - 9780780389922
T3 - IEEE International Integrated Reliability Workshop Final Report
SP - 103
EP - 106
BT - 2005 IEEE International Integrated Reliability Workshop Final Report, IIRW 2005
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2005 IEEE International Integrated Reliability Workshop, IIRW 2005
Y2 - 17 October 2005 through 20 October 2005
ER -