TY - GEN
T1 - An FPGA-based pattern classifier using data compression
AU - Ratsaby, Joel
AU - Zavielov, Denis
PY - 2010
Y1 - 2010
N2 - We implement a text-classification engine on a single FPGA chip running on a 50 Mhz clock. It is based on arithmetic coding data compression. The text classifier is based on the non-parametric nearest-neighbor algorithm. It computes a compression-based distance between two text files. We have devised a parallel hardware architecture for the computation of the tag-interval that encodes the data sequence in arithmetic coding. This architecture achieves a large speedup factor. Even with a relatively slow 50 Mhz clock the hardware solution performs 26 times faster than a software-based implementation of this classifier in C++ on a Pentium® D CPU running on a 3 Ghz clock. There are many applications where such a hardware-based classifier is an advantage not only because of its high speed of execution but because it can be embedded as a single chip into small special-purpose systems with limited computational resources. For instance, on a communication board (passively monitoring network traffic and classifying anomalous patterns), on a CCTV camera (classifying abnormal behavior for homeland security), on a satellite to do real-time classification of high resolution images and on a small-scale weapon that requires real-time target classification. Since we use a universal-distance computed by data compression once a corpus of labeled texts is uploaded onto the chip there is no need for any feature extraction or machine learning.
AB - We implement a text-classification engine on a single FPGA chip running on a 50 Mhz clock. It is based on arithmetic coding data compression. The text classifier is based on the non-parametric nearest-neighbor algorithm. It computes a compression-based distance between two text files. We have devised a parallel hardware architecture for the computation of the tag-interval that encodes the data sequence in arithmetic coding. This architecture achieves a large speedup factor. Even with a relatively slow 50 Mhz clock the hardware solution performs 26 times faster than a software-based implementation of this classifier in C++ on a Pentium® D CPU running on a 3 Ghz clock. There are many applications where such a hardware-based classifier is an advantage not only because of its high speed of execution but because it can be embedded as a single chip into small special-purpose systems with limited computational resources. For instance, on a communication board (passively monitoring network traffic and classifying anomalous patterns), on a CCTV camera (classifying abnormal behavior for homeland security), on a satellite to do real-time classification of high resolution images and on a small-scale weapon that requires real-time target classification. Since we use a universal-distance computed by data compression once a corpus of labeled texts is uploaded onto the chip there is no need for any feature extraction or machine learning.
KW - Data compression
KW - FPGA
KW - Nearest-neighbor algorithm
KW - Parallel architecture
UR - http://www.scopus.com/inward/record.url?scp=78651243150&partnerID=8YFLogxK
U2 - 10.1109/EEEI.2010.5662214
DO - 10.1109/EEEI.2010.5662214
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AN - SCOPUS:78651243150
SN - 9781424486809
T3 - 2010 IEEE 26th Convention of Electrical and Electronics Engineers in Israel, IEEEI 2010
SP - 320
EP - 324
BT - 2010 IEEE 26th Convention of Electrical and Electronics Engineers in Israel, IEEEI 2010
T2 - 2010 IEEE 26th Convention of Electrical and Electronics Engineers in Israel, IEEEI 2010
Y2 - 17 November 2010 through 20 November 2010
ER -