TY - GEN
T1 - Reliability simulation and design consideration of high speed ADC circuits
AU - Yan, Baoguang
AU - Qin, Jin
AU - Dai, Jun
AU - Fan, Qingguo
AU - Bernstein, Joseph B.
PY - 2008
Y1 - 2008
N2 - For the first time, a high speed flash ADC is developed for reliability analysis and simulation of analogue and mix-signal circuit. All the three failure mechanisms (NBTI, HCI, TDDB) are quantified with degradation models. The result shows that pMOS degradation especially NBTI is the most detrimental failure mechanism for the normal operation of high speed ADC, which leads to the fault output. Based on the analysis of the reliability-critical parts, reliability improvement approaches are suggested for the reliable design.
AB - For the first time, a high speed flash ADC is developed for reliability analysis and simulation of analogue and mix-signal circuit. All the three failure mechanisms (NBTI, HCI, TDDB) are quantified with degradation models. The result shows that pMOS degradation especially NBTI is the most detrimental failure mechanism for the normal operation of high speed ADC, which leads to the fault output. Based on the analysis of the reliability-critical parts, reliability improvement approaches are suggested for the reliable design.
UR - http://www.scopus.com/inward/record.url?scp=64549155615&partnerID=8YFLogxK
U2 - 10.1109/IRWS.2008.4796102
DO - 10.1109/IRWS.2008.4796102
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AN - SCOPUS:64549155615
SN - 9781424421954
T3 - IEEE International Integrated Reliability Workshop Final Report
SP - 125
EP - 128
BT - 2008 IEEE International Integrated Reliability Workshop Final Report, IRW 2008
T2 - 2008 IEEE International Integrated Reliability Workshop, IRW 2008
Y2 - 12 October 2008 through 16 October 2008
ER -