TY - CHAP
T1 - Physics of Failures (POF) version B for MTBF prediction
AU - Bot, Y.
AU - Bernstein, J. B.
N1 - Publisher Copyright:
© 2015 Taylor & Francis Group, London, UK.
PY - 2014/1/1
Y1 - 2014/1/1
N2 - In this article we will presents a method for predicting the failure rate, MTBF, and thus the reliability of an electronic system by summing the failure rates of each known failure mechanism, as specified in the JEDEC standard JEP-122G. We use a competing acceleration factor methodology by combining the physics of failure for each mechanism with their effects as observed by High/Low temperature and High/Low voltage stresses. Our new method assumes that lifetime of each of its failure mechanisms follows constant rate distribution and each mechanism is independently accelerated by the stress factors, which include also frequency, current, and other factors that can be entered into a reliability model. The overall failure rate also follows an exponential distribution and is described in the standard FIT (Failure unIT or Failure in Time). The method combines mathematical models for the known failure mechanism and solves them simultaneously at a multiplicity of accelerated life tests to find a consistent set of weighting factors for each mechanism. The result of solving the system of equations is a more accurate and a unique combination for each system model by proportional summation of each of the contributing failure mechanisms. This method is applied to board design using our established parameters based on the chip technology and to chip manufacturers by matching HTOL Data with the foundry’s reliability models.
AB - In this article we will presents a method for predicting the failure rate, MTBF, and thus the reliability of an electronic system by summing the failure rates of each known failure mechanism, as specified in the JEDEC standard JEP-122G. We use a competing acceleration factor methodology by combining the physics of failure for each mechanism with their effects as observed by High/Low temperature and High/Low voltage stresses. Our new method assumes that lifetime of each of its failure mechanisms follows constant rate distribution and each mechanism is independently accelerated by the stress factors, which include also frequency, current, and other factors that can be entered into a reliability model. The overall failure rate also follows an exponential distribution and is described in the standard FIT (Failure unIT or Failure in Time). The method combines mathematical models for the known failure mechanism and solves them simultaneously at a multiplicity of accelerated life tests to find a consistent set of weighting factors for each mechanism. The result of solving the system of equations is a more accurate and a unique combination for each system model by proportional summation of each of the contributing failure mechanisms. This method is applied to board design using our established parameters based on the chip technology and to chip manufacturers by matching HTOL Data with the foundry’s reliability models.
UR - https://www.scopus.com/pages/publications/84906689276
U2 - 10.1201/b17399-122
DO - 10.1201/b17399-122
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AN - SCOPUS:84906689276
SN - 9781138026810
T3 - Safety and Reliability: Methodology and Applications - Proceedings of the European Safety and Reliability Conference, ESREL 2014
SP - 863
EP - 866
BT - Safety and Reliability
T2 - European Safety and Reliability Conference, ESREL 2014
Y2 - 14 September 2014 through 18 September 2014
ER -