TY - GEN
T1 - Multi-queued network processors for packets with heterogeneous processing requirements
AU - Kogan, Kirill
AU - López-Ortiz, Alejandro
AU - Nikolenko, Sergey I.
AU - Sirotkin, Alexander V.
PY - 2013
Y1 - 2013
N2 - Modern network processors (NPs) increasingly deal with packets with heterogeneous processing requirements. In this work, we consider the fundamental problem of managing a bounded size buffer at the input queue of an NP. Incoming traffic consists of packets, each packet requiring several rounds of processing before it can be transmitted out of the queue. The objective is to maximize the total number of successfully transmitted packets. In such an environment, it is well known that Shortest-Remaining-Processing-Time (SRPT) first scheduling with push-out is optimal [1]. However, it is hard to implement both priority queueing (PQ) by remaining processing and the push-out mechanism simultaneously in an NP. We explore alternatives for this architecture, addressing the simplicity vs. performance system design tradeoffs. We design a simplified architecture and provide worst-case guarantees for its throughput performance in different settings. We also conduct a comprehensive simulation study that validates our results.
AB - Modern network processors (NPs) increasingly deal with packets with heterogeneous processing requirements. In this work, we consider the fundamental problem of managing a bounded size buffer at the input queue of an NP. Incoming traffic consists of packets, each packet requiring several rounds of processing before it can be transmitted out of the queue. The objective is to maximize the total number of successfully transmitted packets. In such an environment, it is well known that Shortest-Remaining-Processing-Time (SRPT) first scheduling with push-out is optimal [1]. However, it is hard to implement both priority queueing (PQ) by remaining processing and the push-out mechanism simultaneously in an NP. We explore alternatives for this architecture, addressing the simplicity vs. performance system design tradeoffs. We design a simplified architecture and provide worst-case guarantees for its throughput performance in different settings. We also conduct a comprehensive simulation study that validates our results.
KW - buffer management
KW - competitive analysis
KW - online algorithms
KW - routers
KW - scheduling
UR - http://www.scopus.com/inward/record.url?scp=84874773130&partnerID=8YFLogxK
U2 - 10.1109/COMSNETS.2013.6465538
DO - 10.1109/COMSNETS.2013.6465538
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AN - SCOPUS:84874773130
SN - 9781467354943
T3 - 2013 5th International Conference on Communication Systems and Networks, COMSNETS 2013
BT - 2013 5th International Conference on Communication Systems and Networks, COMSNETS 2013
T2 - 2013 5th International Conference on Communication Systems and Networks, COMSNETS 2013
Y2 - 7 January 2013 through 10 January 2013
ER -