Impact of device scaling on deep sub-micron transistor reliability - A study of reliability trends using SRAM

Mark White; Huang Bing; Qin Jin; Zvi Gur; Michael Talmor; Chen Yuan; Jason Heidecker; Duc Nguyen; Joseph Bernstein

doi:10.1109/IRWS.2005.1609574

Impact of device scaling on deep sub-micron transistor reliability - A study of reliability trends using SRAM

Mark White, Huang Bing, Qin Jin, Zvi Gur, Michael Talmor, Chen Yuan, Jason Heidecker, Duc Nguyen, Joseph Bernstein

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

2 Scopus citations

Abstract

As microelectronics are scaled in to the deep submicron regime, users of advanced technology CMOS, particularly in high-reliability applications, should reassess how scaling effects impact long-term reliability. An experimental based reliability study of industrial grade SRAMs, consisting of three different technology nodes, is proposed to substantiate current acceleration models for temperature and voltage life-stress relationships. This reliability study utilizes Step-Stress techniques to evaluate memory technologies (0.25μm, 0.1 μm, and 0.13μm) embedded in many of today's high-reliability space/aerospace applications. Two acceleration modeling approaches are presented to relate experimental FIT calculations to Mfr's qualification data.

Original language	English
Title of host publication	2005 IEEE International Integrated Reliability Workshop Final Report, IIRW 2005
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	103-106
Number of pages	4
ISBN (Print)	0780389921, 9780780389922
DOIs	https://doi.org/10.1109/IRWS.2005.1609574
State	Published - 2005
Externally published	Yes
Event	2005 IEEE International Integrated Reliability Workshop, IIRW 2005 - S. Lake Tahoe, CA, United States Duration: 17 Oct 2005 → 20 Oct 2005

Publication series

Name	IEEE International Integrated Reliability Workshop Final Report
Volume	2005
ISSN (Print)	1930-8841
ISSN (Electronic)	2374-8036

Conference

Conference	2005 IEEE International Integrated Reliability Workshop, IIRW 2005
Country/Territory	United States
City	S. Lake Tahoe, CA
Period	17/10/05 → 20/10/05

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10.1109/IRWS.2005.1609574

Cite this

White, M., Bing, H., Jin, Q., Gur, Z., Talmor, M., Yuan, C., Heidecker, J., Nguyen, D., & Bernstein, J. (2005). Impact of device scaling on deep sub-micron transistor reliability - A study of reliability trends using SRAM. In 2005 IEEE International Integrated Reliability Workshop Final Report, IIRW 2005 (pp. 103-106). Article 1609574 (IEEE International Integrated Reliability Workshop Final Report; Vol. 2005). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/IRWS.2005.1609574

White, Mark ; Bing, Huang ; Jin, Qin et al. / Impact of device scaling on deep sub-micron transistor reliability - A study of reliability trends using SRAM. 2005 IEEE International Integrated Reliability Workshop Final Report, IIRW 2005. Institute of Electrical and Electronics Engineers Inc., 2005. pp. 103-106 (IEEE International Integrated Reliability Workshop Final Report).

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title = "Impact of device scaling on deep sub-micron transistor reliability - A study of reliability trends using SRAM",

abstract = "As microelectronics are scaled in to the deep submicron regime, users of advanced technology CMOS, particularly in high-reliability applications, should reassess how scaling effects impact long-term reliability. An experimental based reliability study of industrial grade SRAMs, consisting of three different technology nodes, is proposed to substantiate current acceleration models for temperature and voltage life-stress relationships. This reliability study utilizes Step-Stress techniques to evaluate memory technologies (0.25μm, 0.1 μm, and 0.13μm) embedded in many of today's high-reliability space/aerospace applications. Two acceleration modeling approaches are presented to relate experimental FIT calculations to Mfr's qualification data.",

author = "Mark White and Huang Bing and Qin Jin and Zvi Gur and Michael Talmor and Chen Yuan and Jason Heidecker and Duc Nguyen and Joseph Bernstein",

year = "2005",

doi = "10.1109/IRWS.2005.1609574",

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isbn = "0780389921",

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publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "103--106",

booktitle = "2005 IEEE International Integrated Reliability Workshop Final Report, IIRW 2005",

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note = "2005 IEEE International Integrated Reliability Workshop, IIRW 2005 ; Conference date: 17-10-2005 Through 20-10-2005",

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White, M, Bing, H, Jin, Q, Gur, Z, Talmor, M, Yuan, C, Heidecker, J, Nguyen, D & Bernstein, J 2005, Impact of device scaling on deep sub-micron transistor reliability - A study of reliability trends using SRAM. in 2005 IEEE International Integrated Reliability Workshop Final Report, IIRW 2005., 1609574, IEEE International Integrated Reliability Workshop Final Report, vol. 2005, Institute of Electrical and Electronics Engineers Inc., pp. 103-106, 2005 IEEE International Integrated Reliability Workshop, IIRW 2005, S. Lake Tahoe, CA, United States, 17/10/05. https://doi.org/10.1109/IRWS.2005.1609574

Impact of device scaling on deep sub-micron transistor reliability - A study of reliability trends using SRAM. / White, Mark; Bing, Huang; Jin, Qin et al.
2005 IEEE International Integrated Reliability Workshop Final Report, IIRW 2005. Institute of Electrical and Electronics Engineers Inc., 2005. p. 103-106 1609574 (IEEE International Integrated Reliability Workshop Final Report; Vol. 2005).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AB - As microelectronics are scaled in to the deep submicron regime, users of advanced technology CMOS, particularly in high-reliability applications, should reassess how scaling effects impact long-term reliability. An experimental based reliability study of industrial grade SRAMs, consisting of three different technology nodes, is proposed to substantiate current acceleration models for temperature and voltage life-stress relationships. This reliability study utilizes Step-Stress techniques to evaluate memory technologies (0.25μm, 0.1 μm, and 0.13μm) embedded in many of today's high-reliability space/aerospace applications. Two acceleration modeling approaches are presented to relate experimental FIT calculations to Mfr's qualification data.

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White M, Bing H, Jin Q, Gur Z, Talmor M, Yuan C et al. Impact of device scaling on deep sub-micron transistor reliability - A study of reliability trends using SRAM. In 2005 IEEE International Integrated Reliability Workshop Final Report, IIRW 2005. Institute of Electrical and Electronics Engineers Inc. 2005. p. 103-106. 1609574. (IEEE International Integrated Reliability Workshop Final Report). doi: 10.1109/IRWS.2005.1609574

Impact of device scaling on deep sub-micron transistor reliability - A study of reliability trends using SRAM

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