TY - JOUR
T1 - Diode-capacitor voltage multipliers combined with boost-converters
T2 - Topologies and characteristics
AU - Axelrod, B.
AU - Berkovich, Y.
AU - Shenkman, A.
AU - Golan, G.
PY - 2012/7
Y1 - 2012/7
N2 - Various topological modifications of diode-capacitor voltage multipliers are considered. All the topologies are based on two known schemes: Cockcroft-Walton and Dickson. These topologies are built combined with a boost-converter, operating at a high switching frequency. Such a solution allows reducing the values of the capacitors. The proposed topologies can also be used by feeding them directly from a three-phase network through the regular rectifier; in this case the influence of such circuits on a supply network is reduced. A number of novel modifications of multipliers, having their specific features, are obtained. The procedure of calculating the output voltage, depending on the capacitor values and load parameters is proposed and the design formulas for the output voltage of some of the schemes are developed. It is shown that a decrease in the output voltage is caused by some sort of internal resistance. The essentially similar operating modes of different topologies are characterised by a different value of such a resistance, and accordingly by a different internal voltage drop. Dynamic models for some of the proposed topologies are also developed. The computer simulation and the experimental results proved the theoretical expectations.
AB - Various topological modifications of diode-capacitor voltage multipliers are considered. All the topologies are based on two known schemes: Cockcroft-Walton and Dickson. These topologies are built combined with a boost-converter, operating at a high switching frequency. Such a solution allows reducing the values of the capacitors. The proposed topologies can also be used by feeding them directly from a three-phase network through the regular rectifier; in this case the influence of such circuits on a supply network is reduced. A number of novel modifications of multipliers, having their specific features, are obtained. The procedure of calculating the output voltage, depending on the capacitor values and load parameters is proposed and the design formulas for the output voltage of some of the schemes are developed. It is shown that a decrease in the output voltage is caused by some sort of internal resistance. The essentially similar operating modes of different topologies are characterised by a different value of such a resistance, and accordingly by a different internal voltage drop. Dynamic models for some of the proposed topologies are also developed. The computer simulation and the experimental results proved the theoretical expectations.
UR - http://www.scopus.com/inward/record.url?scp=84865849815&partnerID=8YFLogxK
U2 - 10.1049/iet-pel.2011.0215
DO - 10.1049/iet-pel.2011.0215
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AN - SCOPUS:84865849815
SN - 1755-4535
VL - 5
SP - 873
EP - 884
JO - IET Power Electronics
JF - IET Power Electronics
IS - 6
ER -