TY - GEN
T1 - Combined channel segmentation and buffer insertion for routability and performance improvement of field programmable analog arrays
AU - Huang, Hu
AU - Bernstein, Joseph B.
AU - Peckerar, Martin
AU - Luo, Ji
PY - 2004
Y1 - 2004
N2 - In this paper, we propose a combined channel segmentation and buffer insertion approach, which minimizes the number of buffers inserted while satisfying the delay constraints for routing channels of field-programmable analog arrays. A segmented routing algorithm based on minimum-cost-bipartite- matching is improved with demand awareness and used to evaluate the various routing channels generated. Experiments show that, compared to a sequential segmenting-then-buffering design, our approach can significantly reduce the total number of buffers required, while achieving improved routability and minimum average interconnect delay. It is also shown that by increasing the number of long segment appropriately, the algorithm can dramatically improve the routability with a moderate increase on the number of buffers.
AB - In this paper, we propose a combined channel segmentation and buffer insertion approach, which minimizes the number of buffers inserted while satisfying the delay constraints for routing channels of field-programmable analog arrays. A segmented routing algorithm based on minimum-cost-bipartite- matching is improved with demand awareness and used to evaluate the various routing channels generated. Experiments show that, compared to a sequential segmenting-then-buffering design, our approach can significantly reduce the total number of buffers required, while achieving improved routability and minimum average interconnect delay. It is also shown that by increasing the number of long segment appropriately, the algorithm can dramatically improve the routability with a moderate increase on the number of buffers.
UR - http://www.scopus.com/inward/record.url?scp=17644380009&partnerID=8YFLogxK
U2 - 10.1109/ICCD.2004.1347966
DO - 10.1109/ICCD.2004.1347966
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AN - SCOPUS:17644380009
SN - 0769522319
T3 - Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors
SP - 490
EP - 495
BT - Proceedings - IEEE International Conference on Computer Design
T2 - Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors, ICCD 2004
Y2 - 11 October 2004 through 13 October 2004
ER -