Combined channel segmentation and buffer insertion for routability and performance improvement of field programmable analog arrays

Hu Huang, Joseph B. Bernstein, Martin Peckerar, Ji Luo

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

2 Scopus citations

Abstract

In this paper, we propose a combined channel segmentation and buffer insertion approach, which minimizes the number of buffers inserted while satisfying the delay constraints for routing channels of field-programmable analog arrays. A segmented routing algorithm based on minimum-cost-bipartite- matching is improved with demand awareness and used to evaluate the various routing channels generated. Experiments show that, compared to a sequential segmenting-then-buffering design, our approach can significantly reduce the total number of buffers required, while achieving improved routability and minimum average interconnect delay. It is also shown that by increasing the number of long segment appropriately, the algorithm can dramatically improve the routability with a moderate increase on the number of buffers.

Original languageEnglish
Title of host publicationProceedings - IEEE International Conference on Computer Design
Subtitle of host publicationVLSI in Computers and Processors, ICCD 2004
Pages490-495
Number of pages6
DOIs
StatePublished - 2004
Externally publishedYes
EventProceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors, ICCD 2004 - San Jose, CA, United States
Duration: 11 Oct 200413 Oct 2004

Publication series

NameProceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors
ISSN (Print)1063-6404

Conference

ConferenceProceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors, ICCD 2004
Country/TerritoryUnited States
CitySan Jose, CA
Period11/10/0413/10/04

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