TY - JOUR
T1 - Characterization of transient gate oxide trapping in SiC MOSFETs using fast I-V techniques
AU - Gurfinkel, Moshe
AU - Xiong, Hao D.
AU - Cheung, Kin P.
AU - Suehle, John S.
AU - Bernstein, Joseph B.
AU - Shapira, Yoram
AU - Lelis, Aivars J.
AU - Habersat, Daniel
AU - Goldsman, Neil
N1 - Funding Information:
Manuscript received October 1, 2007; revised April 8, 2008. This work was supported in part by the National Institute of Standards and Technology (NIST) Office of Microelectronics Programs and in part by the Office of Naval Research. The review of this paper was arranged by Editor G. Pensl. M. Gurfinkel and Y. Shapira are with the School of Electrical Engineering, Tel Aviv University, Tel Aviv 69978, Israel (e-mail: [email protected]). H. D. Xiong, K. P. Cheung, and J. S. Suehle are with the National Institute of Standards and Technology, Gaithersburg, MD 20899 USA. J. B. Bernstein is with Bar-Ilan University, Ramat-Gan 52900, Israel, and also with the Department of Mechanical Engineering, University of Maryland, College Park, MD 20742 USA. A. J. Lelis and D. Habersat are with the Army Research Laboratories, Adelphi, MD 20783 USA. N. Goldsman is with the Department of Electrical and Computer Engineering, University of Maryland, College Park, MD 20742 USA. Digital Object Identifier 10.1109/TED.2008.926626
PY - 2008
Y1 - 2008
N2 - Threshold voltage and drain current instabilities in state-of-the-art 4H-SiC MOSFETs with thermal as-grown SiO2 and NO-annealed gate oxides have been studied using fast I-V measurements. These measurements reveal the full extent of the instability underestimated by dc measurements. Furthermore, fast measurements allow the separation of negative and positive bias stress effects. Postoxidation annealing in NO was found to passivate the oxide traps and dramatically reduce the instability. A physical model involving fast transient charge trapping and detrapping at and near the SiC/SiO2interface is proposed.
AB - Threshold voltage and drain current instabilities in state-of-the-art 4H-SiC MOSFETs with thermal as-grown SiO2 and NO-annealed gate oxides have been studied using fast I-V measurements. These measurements reveal the full extent of the instability underestimated by dc measurements. Furthermore, fast measurements allow the separation of negative and positive bias stress effects. Postoxidation annealing in NO was found to passivate the oxide traps and dramatically reduce the instability. A physical model involving fast transient charge trapping and detrapping at and near the SiC/SiO2interface is proposed.
KW - Annealing
KW - Charge carrier processes
KW - Reliability
KW - Silicon carbide
KW - Transient trapping
UR - http://www.scopus.com/inward/record.url?scp=49349084034&partnerID=8YFLogxK
U2 - 10.1109/TED.2008.926626
DO - 10.1109/TED.2008.926626
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AN - SCOPUS:49349084034
SN - 0018-9383
VL - 55
SP - 2004
EP - 2012
JO - IEEE Transactions on Electron Devices
JF - IEEE Transactions on Electron Devices
IS - 8
ER -