TY - GEN
T1 - Adaptive clock gating for shift register based circuits
AU - Wimer, Shmuel
AU - Koren, Israel
AU - Cohen, Itamar
PY - 2010
Y1 - 2010
N2 - Clock gating is a widely used technique for dynamic power reduction in VLSI design. In its most straightforward application it allows disabling the clock signal of a flip-flop once its state is no longer subject to changes. This paper extends this technique one step further and proposes a systematic way to achieve additional dynamic power savings based on the correlation of flip-flops' activities. Circuits based on shift registers are widely used in digital systems and we selected them to demonstrate the effectiveness of the proposed method. The best, worst and average cases for dynamic power savings tare analyzed.
AB - Clock gating is a widely used technique for dynamic power reduction in VLSI design. In its most straightforward application it allows disabling the clock signal of a flip-flop once its state is no longer subject to changes. This paper extends this technique one step further and proposes a systematic way to achieve additional dynamic power savings based on the correlation of flip-flops' activities. Circuits based on shift registers are widely used in digital systems and we selected them to demonstrate the effectiveness of the proposed method. The best, worst and average cases for dynamic power savings tare analyzed.
UR - http://www.scopus.com/inward/record.url?scp=78651226114&partnerID=8YFLogxK
U2 - 10.1109/EEEI.2010.5662200
DO - 10.1109/EEEI.2010.5662200
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AN - SCOPUS:78651226114
SN - 9781424486809
T3 - 2010 IEEE 26th Convention of Electrical and Electronics Engineers in Israel, IEEEI 2010
SP - 374
EP - 378
BT - 2010 IEEE 26th Convention of Electrical and Electronics Engineers in Israel, IEEEI 2010
T2 - 2010 IEEE 26th Convention of Electrical and Electronics Engineers in Israel, IEEEI 2010
Y2 - 17 November 2010 through 20 November 2010
ER -