A reliability evaluation methodology for memory chips for space applications when sample size is small

Y. Chen, D. Nguyen, S. Guertin, J. Bernstein, M. White, R. Menke, S. Kayali

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

5 Scopus citations

Abstract

This paper presents a reliability evaluation methodology to obtain the statistical reliability evaluation methodology to obtain the statistical reliability information of memory chips for space applications when the test sample size needs to be kept small because of the high cost of the radiation hardness memories. This methodology can be also used to generate overdriving guidelines and characterize production lines in commercial applications and to obtain de-rating guidelines in space applications.

Original languageEnglish
Title of host publication2003 IEEE International Integrated Reliability Workshop Final Report, IRW 2003
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages91-94
Number of pages4
ISBN (Electronic)0780381572
DOIs
StatePublished - 2003
Externally publishedYes
Event2003 IEEE International Integrated Reliability Workshop, IRW 2003 - Lake Tahoe, United States
Duration: 20 Oct 200323 Oct 2003

Publication series

NameIEEE International Integrated Reliability Workshop Final Report
Volume2003-January
ISSN (Print)1930-8841
ISSN (Electronic)2374-8036

Conference

Conference2003 IEEE International Integrated Reliability Workshop, IRW 2003
Country/TerritoryUnited States
CityLake Tahoe
Period20/10/0323/10/03

Keywords

  • Acceleration
  • Costs
  • Educational institutions
  • Guidelines
  • Production
  • Reliability engineering
  • Space missions
  • Space technology
  • Testing
  • Voltage

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