A New High-Volume/Low-Mix Simulation Testbed for Semiconductor Manufacturing

Michael Hassoun, Denny Kopp, Lars Monch, Adar Kalir

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

12 Scopus citations


As part of an effort to present to the semiconductor manufacturing community an updated wafer fab testbed, we provide the first of two simulation models, namely a High-Volume/Low-Mix (HV/LM) fab simulation model. The model is realistic in scale and level of complexity. A full description of the model features is provided, and its performance is studied based on an implementation using the AutoSched AP simulation tool. The simulation model is made publicly available online to allow researchers as well as practitioners to gain hands-on experience with it, and hopefully validate its features, or propose changes if needed. A final version of the testbed, including a low-volume/high-mix wafer fab simulation model will be presented within a year.

Original languageEnglish
Title of host publication2019 Winter Simulation Conference, WSC 2019
PublisherInstitute of Electrical and Electronics Engineers Inc.
Number of pages10
ISBN (Electronic)9781728132839
StatePublished - Dec 2019
Event2019 Winter Simulation Conference, WSC 2019 - National Harbor, United States
Duration: 8 Dec 201911 Dec 2019

Publication series

NameProceedings - Winter Simulation Conference
ISSN (Print)0891-7736


Conference2019 Winter Simulation Conference, WSC 2019
Country/TerritoryUnited States
CityNational Harbor


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