TY - GEN
T1 - Parallel processing algorithm for Bayesian network inference
AU - Kaspi, Gil
AU - Ratsaby, Joel
PY - 2012
Y1 - 2012
N2 - We introduce an algorithm for Bayesian network inference using parallel computations that perform variable-elimination over multiple threads of execution. The algorithm can be implemented on a collection of parallel execution entities on a single FPGA. Each execution entity performs addition and multiplication. Relative to the standard bucket elimination, the parallel algorithm reduces the computational time by an amount that depends on the coupling (probabilistic dependency) of the network and on the evidence available at time of prediction query.
AB - We introduce an algorithm for Bayesian network inference using parallel computations that perform variable-elimination over multiple threads of execution. The algorithm can be implemented on a collection of parallel execution entities on a single FPGA. Each execution entity performs addition and multiplication. Relative to the standard bucket elimination, the parallel algorithm reduces the computational time by an amount that depends on the coupling (probabilistic dependency) of the network and on the evidence available at time of prediction query.
UR - http://www.scopus.com/inward/record.url?scp=84871980029&partnerID=8YFLogxK
U2 - 10.1109/EEEI.2012.6377114
DO - 10.1109/EEEI.2012.6377114
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AN - SCOPUS:84871980029
SN - 9781467346801
T3 - 2012 IEEE 27th Convention of Electrical and Electronics Engineers in Israel, IEEEI 2012
BT - 2012 IEEE 27th Convention of Electrical and Electronics Engineers in Israel, IEEEI 2012
T2 - 2012 IEEE 27th Convention of Electrical and Electronics Engineers in Israel, IEEEI 2012
Y2 - 14 November 2012 through 17 November 2012
ER -